We evaluate the resilience of modern parallel devices for high performance computing applications, i.e. Graphics Processing Units (GPUs), and heterogeneous Systems on Chips, i.e. Accelerated Processing Units. Nowadays the error rate of supercomputers may be extremely high. As we have evaluated with previous experiments at ISIS, the error rate of TITAN, a supercomputer composed of 18,000 GPUs, can be of up to one error every 10 minutes. TITAN personnel confirmed this value. Additionally, we were able to match experimental data gathered at ISIS with TITAN field data, based on more than 1,400 millions GB of data, and 500 millions GPU node hours of operation. Finally, we will study the neutron sensitivity of modern System on Chips embedding ARM core and FPGA programmable logic. We will exploit the FPGA programmability to implement a general-purpose mitigation scheme for the ARM processor.