Semiconductor industry is currently offering 7 nm technology node with FinFET fabrication processes. Soft error causing mechanisms and error rates for FinFET technologies are expected to be vastly different from those for planar technologies. This proposal is for the investigation of neutron-induced soft errors for 7 nm flip-flop and logic circuit designs. We will be using custom-designed test ICs containing multiple hardened and non-hardened FF designs and logic circuits. Since soft errors caused by neutrons are going to dominate all other failure mechanisms, tests are needed to estimate neutron-induced failure rates to allow for development of predictive models. Results from these experiments will be supported with radiation transport simulations and circuit simulations. Results will support a dissertation and will be disseminated through publications at conferences and journals