Soft errors are expected to be the most dominant failure mechanism at 20 nm technology node. With the low critical charge requirements for an upset (~ 0.1 fC), SRAM cells and flip-flop designs are expected to see a sharp increase in soft errors due to muons. We request 5 days of beam time to perform accelerated tests to characterize the probability of soft errors for 28-nm and 20-nm ICs. To investigate this emerging effect, we have assembled a collaboration of industrial partners including Cisco Systems, Marvell Semiconductor, Broadcom, and TSMC. The partners will contribute leading edge microelectronics for test. The results of the experiment will be supplemented with radiation transport simulations and investigations into the impacts on terrestrial and space soft error rates. The investigation will support a doctoral dissertation and be disseminated through publications.